Sr. Engineer, Performance Infrastructure (RISC-V)
Tenstorrent6 hours ago
Responsibilities
- Build and maintain benchmarking automation and CI pipelines running SPEC and real-world workloads across RISC-V silicon, FPGA/emulation platforms, and performance models.
- Own SimPoint generation and management infrastructure.
- Build database-backed performance-data collection, dashboards, and visualization tools for tracking trends and regressions.
- Develop QEMU- and CRIU-based workload capture and replay tooling.
- Collaborate with performance and software engineers to understand workflows and remove infrastructure friction.
Requirements
- Strong Linux systems engineering skills and comfort managing lab machines, clusters, and flaky hardware platforms.
- Proficiency in Python and shell scripting, with experience using GitLab CI and containers.
- Experience automating at scale, including job scheduling, artifact management, databases, and dashboarding.
- Ability to identify problems, develop solutions, and own the systems built.
- Curiosity about CPU performance is beneficial, while deep microarchitecture experience is not required.
Benefits
- Hybrid work based in Austin, Texas, or Santa Clara, California.
- Competitive compensation package and benefits.
- Opportunity to work across pre-silicon and post-silicon performance platforms, including models, emulation, FPGA, and real RISC-V hardware.
About Tenstorrent
Tenstorrent builds AI compute hardware and RISC‑V CPU technology for companies developing training and inference workloads in data centers and at the edge. The business sells accelerator cards and systems with a full software stack, and licenses RISC‑V CPU IP. Founded in 2016 and headquartered in Toronto, it is privately held and led by semiconductor architect Jim Keller.