3 days ago
Santa Clara, CA, USASenior
Base Salary
$204k - $306k/yr
Responsibilities
- Lead development of networking software for GPU scale-up interconnects and Ethernet-based AI fabrics on AMD Helios systems.
- Develop and optimize Linux kernel drivers, embedded firmware, and user-space software for GPU interconnect, NIC, and switch subsystems.
- Drive ASIC and platform bring-up, including SerDes, link initialization, Ethernet MAC/PCS/FEC configuration, topology discovery, and validation.
- Collaborate on switch configuration, forwarding, QoS, telemetry, and fabric management for scale-up and scale-out topologies.
- Define firmware, driver, management interfaces, and control-plane protocols between GPUs, switches, and fabric management software.
- Analyze network performance, latency, bandwidth utilization, congestion behavior, and communication efficiency across multi-node deployments.
- Develop diagnostics and telemetry tools to monitor fabric health, identify bottlenecks, and accelerate root-cause analysis.
- Resolve issues spanning GPUs, NICs, switches, transport layers, firmware, drivers, collective communication libraries, and distributed runtimes.
- Contribute to resiliency, reliability, availability, serviceability, and deployment-readiness features for large-scale clusters.
- Support performance characterization of collective operations and distributed training and inference workloads.
- Partner with internal teams and external switch and platform vendors to validate interoperability and optimize AI workload performance.
- Provide technical leadership through design and code reviews, mentorship, and cross-team technical direction.
Requirements
- Strong C and C++ programming skills; Python or Go experience for tooling is a plus.
- Experience developing Linux kernel drivers for PCIe devices, including DMA, interrupts, and memory management.
- Experience developing embedded firmware on microcontrollers or SoC management processors in RTOS or bare-metal environments.
- Strong knowledge of Ethernet MAC, PCS, FEC, SerDes, link training, auto-negotiation, L2 switching, bridging, VLANs, MAC learning, LLDP, link aggregation, L3 forwarding, and QoS.
- Experience with GPU interconnect or scale-up technologies such as UALink, Infinity Fabric/xGMI, NVLink, or Ethernet-based scale-up.
- Experience with datacenter switch software such as SONiC, SAI, or switch ASIC SDKs.
- Experience with RDMA, RoCE, InfiniBand, TCP/IP, or related high-performance transport technologies.
- Familiarity with scale-up and scale-out architectures in AI or large distributed computing environments.
- Experience debugging complex multi-node issues across hardware, firmware, drivers, switches, and application workloads.
- Experience with performance analysis, profiling, tracing, and observability tools for system and network tuning.
- ASIC, GPU, NIC, or switch bring-up experience is highly desirable.
- Knowledge of reliability, availability, and serviceability considerations in rack-scale or datacenter deployments is a plus.
- Experience with debuggers and source code control tools.
- Effective communication and problem-solving skills, with the ability to lead technical work across architecture, hardware, firmware, software, and validation teams.
- Bachelor's or master's degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent.
Benefits
- The position is located in Santa Clara, California.
- AMD states that benefits are offered and described in its benefits overview.
- This role is not eligible for visa sponsorship.
About AMD
AMD designs and sells CPUs, GPUs, and adaptive/embedded computing products for PCs, data centers, gaming, and edge devices. Its portfolio includes Ryzen and EPYC processors, Radeon and Instinct graphics, and adaptive SoCs from its Xilinx acquisition, sold to OEMs, cloud providers, and device makers. Founded in 1969 and headquartered in Santa Clara, it is a public company on NASDAQ and supplies semi-custom chips for major game consoles.