Qualcomm

Software Engineer — RISC-V Random Test Generator & Assembler Infrastructure

Qualcomm
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2 days ago
Cupertino, CA, USAMid Level / Senior
H1B Sponsor

Base Salary

$167k - $251k/yr

Responsibilities

  • Implement generation objects for RISC-V extensions, micro-architectural scenarios, and composable data/control-flow idioms.
  • Add and verify instruction forms and encodings in the Python companion assembler.
  • Create and tune generation themes to improve RTL coverage.
  • Develop privileged-software sequences for exception and interrupt handling, page-table construction, PMP configuration, and IMSIC programming.
  • Collaborate with ISS and RTL verification engineers to triage failures, add regression scenarios, and adjust register-allocation, address-space, and data-filler constraints.

Requirements

  • Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field plus 4+ years of relevant experience; alternatively, a master’s degree plus 3+ years or a PhD plus 2+ years.
  • 2–5 years of experience in CPU design verification, ISS development, or hardware-software co-design.
  • Strong Python 3 skills, including generator-based coroutines and object-oriented design patterns.
  • Working knowledge of the RISC-V ISA, instruction encodings, CSR semantics, privilege levels, and the memory model; comparable x86 or ARM knowledge is an alternative.
  • Familiarity with virtual memory, PMP, and trap/interrupt handling.
  • Exposure to random test-generation flows or ISS/RTL co-simulation is preferred.
  • Compiler development experience, hypervisor or AIA/IMSIC knowledge, and familiarity with constraint-propagation libraries are preferred.

Benefits

  • Annual discretionary bonus program and potential annual RSU grants.
  • Competitive benefits package supporting employees at work, at home, and at play.
  • Qualcomm equal opportunity employer with workplace and hiring accommodations available for individuals with disabilities.

Tech Stack

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Qualcomm

About Qualcomm

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