Samsung Semiconductor

Develop and optimize trace-driven power and thermal simulation engines that integrate power models, workload traces, and thermal solvers. This senior role focuses on scalable, high-performance C++ simulation infrastructure and system-level hotspot analysis.

Lead performance engineering for production-scale AI workloads, analyzing distributed inference, agentic workflows, and hardware-software interactions to identify bottlenecks and guide future computing platforms. This Senior Staff role sets benchmarking direction across hardware architects, systems engineers, and software researchers.

Lead development of large-scale, interactive web-based visualization tools that help engineers understand AI/ML performance and diagnose inference bottlenecks. This staff-level role bridges frontend engineering, profiling data, developer tooling, and computer architecture.

Technical Director, Large-Scale AI Model Inferencing is a hands-on technical authority defining memory-centric inference solutions for frontier AI models at production scale. The role connects model architecture, inference software, GPU and memory systems, and product strategy to improve capacity, performance, and cost.

Develop and optimize trace-driven power and thermal simulation engines that integrate power models, workload traces, and thermal solvers. This onsite San Jose role focuses on scalable, reproducible simulation infrastructure and advanced hotspot analysis.

Lead the architecture of AI-focused NAND and SSD storage systems by connecting real-world inference workloads to storage, memory-hierarchy, and data-placement innovations. This hands-on technical leadership role spans AI runtimes, Linux storage and networking, SSD firmware, and hardware.

Lead firmware test engineering for NVMe SSDs, developing black-box functional coverage, debugging failures, and addressing customer field issues. This onsite San Jose role combines deep storage-domain expertise with scripting and Linux proficiency.

Build and optimize the EDA design environments, HPC infrastructure, and enterprise tooling that support semiconductor design organizations at scale. This senior technical role drives infrastructure standards, compute efficiency, license optimization, and engineering productivity.

Lead the design and implementation of compiler infrastructure that enables AI/ML workloads to run efficiently on novel hardware. This Staff Engineer role spans kernel DSLs, MLIR-based lowering, scheduling, memory placement, and upstream open-source contributions.