Software Engineer, Chip Design
Ricursive Intelligence4 hours ago
Palo Alto, CA, USAMid Level
Responsibilities
- Develop and scale infrastructure for the end-to-end RTL-to-GDSII flow, including hierarchical designs, advanced process nodes, and complex constraints.
- Build reliable systems for running and orchestrating multi-stage design flows across different EDA tools.
- Productize cutting-edge algorithms for production chip design workflows.
- Analyze timing violations, congestion, routing issues, and other design metrics to improve flow convergence and PPA.
- Deploy AI-driven methods for design analysis, optimization, and iteration.
Requirements
- Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field.
- Strong programming skills in Python, C++, Java, or a comparable language.
- Working understanding of the digital chip design flow from RTL through physical design and signoff.
- Experience integrating, automating, or orchestrating EDA tools in larger engineering workflows.
- Ability to take ownership of ambiguous technical problems, learn unfamiliar areas quickly, and deliver production solutions.
- Preferred: Master’s or PhD in Computer Science, Electrical Engineering, or a related technical field.
- Preferred: Experience with EDA, semiconductor design, distributed systems, or optimization.
- Preferred: Familiarity with placement, timing analysis, RC extraction, or netlist processing algorithms.
- Preferred: Quantified experience demonstrating PPA benefits from AI/ML tooling, AI-driven optimization, ML QoR prediction, or LLM-based flow automation.
About Ricursive Intelligence
A frontier AI lab enabling a recursive self-improvement loop between AI and the chips that fuel it.