Ricursive Intelligence

Software Engineer, Chip Design

Ricursive Intelligence
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1 month ago
Palo Alto, CA, USAEntry Level

Responsibilities

  • Develop and scale infrastructure for the chip design flow, including support for hierarchical design, advanced process nodes, and complex constraints.
  • Analyze timing violations, congestion, routing issues, and other design metrics to improve flow convergence and PPA.
  • Deploy AI-driven methods to automate design analysis, optimization, and iteration across the chip design flow.
  • Debug issues at scale and make engineering tradeoffs involving quality, runtime, robustness, and deadlines.

Requirements

  • Bachelor’s degree in Computer Science, Electrical Engineering, or a related technical field.
  • Strong programming skills in Python, C++, Java, or a comparable language.
  • Comfort using modern AI-assisted development tools to navigate codebases, debug problems, and accelerate engineering workflows.
  • Working understanding of digital chip design from RTL through physical design and signoff.
  • Ability to take ownership of ambiguous technical problems, ramp quickly in unfamiliar areas, and drive work through production.
  • Preferred: Master’s or PhD in Computer Science, Electrical Engineering, or a related technical field.
  • Preferred: experience with semiconductor design, distributed systems, or optimization.
  • Preferred: familiarity with placement, timing analysis, RC extraction, netlist processing, or other chip design automation algorithms.
  • Preferred: demonstrated and quantified PPA benefits from AI/ML tooling.

Tech Stack

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Ricursive Intelligence

About Ricursive Intelligence

11-50 employees

Ricursive Intelligence builds AI systems that co-optimize machine learning models and the chips that run them, starting with AI-driven chip design tools for semiconductor and AI hardware teams. Its business focuses on software and research that closes the loop between model performance and silicon layout to accelerate development cycles. Privately held and founded in 2025, it operates at the intersection of AI infrastructure and semiconductor design.

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