Senior Embedded Software Engineer - Ethernet Retimers
Astera LabsBase Salary
$133k - $185k/yr
Responsibilities
- Debug firmware behavior across Ethernet configurations, link states, and failure modes with the system validation team.
- Investigate and fix embedded C firmware issues involving PHY, SERDES, FEC/PCS, MAC, and retimer interactions.
- Triage issues and drive them to resolution while connecting firmware and system validation teams.
- Support customer bring-up and integration, including field issue triage and coordination of fixes.
- Partner with field applications engineers to diagnose and resolve deployment issues.
- Develop firmware features for SERDES configuration, link training, equalization, and diagnostics.
- Collaborate with SoC, field applications, and platform teams throughout the product lifecycle.
- Help bring Taurus products from initial silicon bring-up through customer deployment.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 5+ years of experience in firmware development or embedded systems engineering.
- Hands-on experience with Ethernet at the system or device level, including technologies such as PHY, SERDES, retimers, gearboxes, NICs, or switches.
- Strong embedded C/C++ skills and experience working in a firmware codebase on real hardware.
- Ability to debug across the hardware/software boundary, including register accesses, embedded SDKs, link state machines, PHY telemetry, and debug logs.
- Familiarity with Linux development tools including gcc or clang, make, bash, gdb, and git.
- Experience with switch or NIC management software, SAI, or OpenBMC is preferred.
- Knowledge of PMA, FEC, or other PHY-layer subsystems beyond SERDES is preferred.
- Background with retimer or gearbox firmware or SDK/API development is preferred.
- Python scripting experience for debugging, test automation, or data analysis is preferred.
- Experience with BERTs, oscilloscopes, or Viavi, Lecroy, Exfo, Keysight, or Tektronix lab equipment is preferred.
- Understanding of signal integrity concepts including equalization, jitter, eye diagrams, and link margin is preferred.
- Prior experience mentoring engineers or leading cross-team debugging efforts is preferred.
- Strong communication skills and comfort working in a fast-moving environment are required.
Benefits
- Eligible for discretionary bonus, incentives, and benefits.
- The posting does not specify a work arrangement or contract duration.
About Astera Labs
Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink™ Fusion, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.