11 months ago
Remote, United States +3 moreMid Level
Responsibilities
- Extend compiler IRs to represent algorithms involving control flow and iterative computation beyond DNN graphs.
- Develop compilation strategies that unify analog compute with digital subsystems while maintaining performance and correctness.
- Prototype and optimize irregular or dynamic-control-flow algorithms using vectorization, predication, and scheduling.
- Collaborate with hardware engineers to co-design ISA and execution-model features for algorithmic workloads.
- Define higher-level programming abstractions and a roadmap to simplify prototyping and accelerate deployment.
Requirements
- At least 3 years of professional experience in compilers or high-performance systems software.
- Proficiency in modern C++ and Python.
- Familiarity with compiler IRs such as MLIR, LLVM, or equivalent systems for representing complex program structures.
- A solid foundation in program analysis and optimization techniques, including SSA form, loop optimization, and vectorization.
- Preferred experience developing MLIR or LLVM control-flow or affine/polyhedral dialects.
- Preferred experience with compiler-hardware co-design and refining ISA or execution models.
- Preferred experience optimizing irregular or control-flow-heavy algorithms in compiler IRs.
- Preferred experience extending ML compiler stacks such as ONNX, IREE, XLA, PyTorch, or TVM beyond DNN workloads.
Benefits
- Opportunity to make algorithmic and control-flow-heavy workloads practical on novel accelerator hardware.
- Role combining compiler design and hardware co-design and influencing accelerator architecture.
- Collaborative and innovative engineering environment with emphasis on rigor, continuous integration, and user-focused design.
- Competitive compensation, equity, and benefits package.
