Principal Product Engineer
Cadence Design Systems1 day ago
Responsibilities
- Support Cadence products in the Digital and Signoff team.
- Track and debug customer issues and collaborate with R&D and release teams on issue resolution.
- Run design benchmarks and develop flows and solutions.
- Provide technical place-and-route expertise to Cadence customers and R&D.
- Apply timing closure and PPA optimization expertise to advanced chip design platforms.
Requirements
- MS in Electrical Engineering with 5+ years of digital implementation experience, or BS in Electrical Engineering with 8+ years of digital implementation experience.
- Strong understanding of VLSI physical design, timing analysis, and RTL-to-GDSII methodologies.
- Familiarity with RTL synthesis, placement optimization, clock tree synthesis, routing optimization, and silicon signoff.
- Experience with industry-standard EDA tools for synthesis, physical design, and signoff at 16nm and below nodes.
- Exposure to hierarchical design methodologies and low-power design.
- Automation skills using Perl, Tcl, and shell scripting.
- Strong analytical, problem-solving, verbal communication, and written communication skills.
Tech Stack
PerlTcl
Categories
Product Engineering
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.