6 days ago
Saratoga, CA, USAStaff+
Responsibilities
- Develop embedded software and firmware for configuring, initializing, calibrating, monitoring, and diagnosing high-speed SerDes PHYs.
- Lead bring-up and optimization of 224G PAM4 SerDes for Ethernet switches, networking products, and accelerators.
- Develop Ethernet, PCIe, and UCIe software for link initialization, training, equalization, lane management, repair, monitoring, recovery, and diagnostics.
- Implement transmitter and receiver adaptation, equalization, calibration, eye optimization, margining, skew management, polarity inversion, lane remapping, and environmental compensation.
- Create APIs, drivers, firmware interfaces, command-line tools, and diagnostic utilities for SerDes control.
- Develop automated characterization and production-test software for PRBS, BER, eye scans, bathtub curves, jitter, signal margin, loopback, lane isolation, and channel characterization.
- Analyze link failures across silicon, package, board, connector, cable, and optical-module channels using telemetry, laboratory measurements, and simulation results.
- Develop runtime health monitoring, telemetry, predictive failure detection, fault recovery, and performance optimization across process, voltage, temperature, channel loss, and manufacturing variation.
- Define reusable software abstractions supporting multiple SerDes IP vendors and PHY generations.
- Create technical specifications, programming guides, bring-up procedures, debug playbooks, and validation plans.
- Mentor engineers and serve as the organization’s technical authority for SerDes software and system bring-up.
Requirements
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Typically 10 or more years of experience in SerDes firmware, PHY software, silicon bring-up, or high-speed interface validation.
- Deep understanding of PAM4 and NRZ signaling, channel loss, insertion loss, return loss, jitter, noise, crosstalk, reflections, clock and data recovery, equalization, BER, eye diagrams, link margin, and forward error correction.
- Hands-on experience bringing up and debugging at least one advanced SerDes generation, preferably 112G or 224G PAM4.
- Experience with Ethernet SerDes and IEEE 802.3 link training, PCIe Gen5/Gen6 or later PHYs, UCIe, or another high-speed die-to-die interface.
- Strong embedded programming skills in C and C++, plus Python or a similar language for automation, characterization, data analysis, and laboratory equipment control.
- Experience programming SerDes registers through MDIO, I²C, SPI, PCIe configuration space, memory-mapped registers, or vendor-specific interfaces.
- Familiarity with embedded processors, microcontrollers, real-time firmware, interrupts, DMA, and hardware/software interfaces.
- Experience debugging pre-silicon models, emulation platforms, FPGA prototypes, and post-silicon devices.
- Ability to interpret schematics, package and board topology, channel models, IBIS-AMI results, and signal-integrity reports.
- Experience using high-bandwidth oscilloscopes, BERTs, VNAs, protocol analyzers, and traffic generators.
- Strong root-cause analysis skills across analog, digital, firmware, package, board, and system domains.
- Preferred experience with 224G Ethernet PHYs, 800G or faster Ethernet systems, PCIe 6.x or PCIe 7.0, UCIe PHY and adapter-layer bring-up, third-party SerDes IP integration, vendor-independent abstraction layers, CMIS, pluggable optics, retimers, active electrical cables, linear-drive optics, SerDes power optimization, field diagnostics, manufacturing-test solutions, advanced process nodes, 2.5D packaging, interposers, and chiplet architectures.
- Track record of technical leadership, cross-functional execution, and mentoring.
Benefits
- The role offers the opportunity to work on AI infrastructure technology intended to improve AI data-center performance, GPU utilization, training completion times, and inference throughput.
- The starting base salary is determined based on skills, experience, qualifications, work location, market trends, and comparable employee compensation; no specific amount is stated.
