Tech Lead– Verification Methodology/CAD
Astera Labs2 months ago
Bengaluru, IndiaStaff+
Responsibilities
- Own verification methodology, CAD, automation, and infrastructure across projects.
- Develop scalable frameworks for simulation, regression, coverage, debug, and verification signoff.
- Build and maintain CAD and automation flows using Python, Tcl, Perl, Shell, and C/C++.
- Automate test generation, compilation, regression execution, result collection, coverage analysis, and reporting.
- Develop infrastructure for large-scale UVM and SystemVerilog verification environments.
- Integrate simulation, lint, CDC/RDC, formal, coverage, and other verification tools into common workflows.
- Improve regression turnaround through parallelization and optimization.
- Develop dashboards and metrics for verification quality, coverage, regression health, and project status.
- Debug infrastructure and tool-flow issues and provide support to verification teams.
- Establish reusable verification components, scripts, libraries, and methodology guidelines.
- Evaluate verification technologies and tools, work with EDA vendors, and support tool-version migrations.
- Define and enforce standards, mentor verification engineers, and drive adoption of common frameworks across teams.
Requirements
- 6–12 years of experience in verification methodology, CAD, and automation.
- Bachelor’s or master’s degree in Electronics, Electrical Engineering, Computer Science, Computer Engineering, VLSI, or a related discipline.
- Strong programming and scripting skills in Python, Tcl, Perl, and Shell; C/C++ preferred.
- Strong understanding of SystemVerilog and UVM.
- Experience with simulation tools such as VCS, Xcelium, or Questa, or equivalent tools.
- Experience building and maintaining regression infrastructure, including coverage collection and analysis.
- Understanding of simulation, UVM, lint, CDC/RDC, formal, code and functional coverage, regression, and debug flows.
- Strong Linux and Unix environment experience.
- Experience with large-scale SoC/IP verification environments and integrating multiple EDA tools is preferred.
- Experience with Jenkins, GitLab CI, distributed or parallel regression infrastructure, and cloud-based or scalable compute environments is preferred.
- Knowledge of databases, dashboards, APIs, or web-based verification infrastructure is advantageous.
- Experience working with EDA vendors and managing tool-flow issues is preferred.
- Ability to provide technical leadership, mentor engineers, and balance immediate project needs with long-term methodology improvements.
Benefits
- The posting encourages applications from people with diverse backgrounds and experiences, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.
About Astera Labs
Astera Labs builds semiconductor-based connectivity solutions and software that link CPUs, GPUs, memory, and storage for AI and cloud data centers, integrating CXL, PCIe, Ethernet, NVLink, and UALink. It offers standards-based and custom connectivity products alongside its COSMOS software suite, serving hyperscalers and server OEMs. Founded in 2017 and headquartered in San Jose, it is a public company listed on Nasdaq under the ticker ALAB.