11 months ago
Remote, United States +3 moreMid Level
Responsibilities
- Develop operator lowering, graph and IR transformations, optimization passes, and backend code generation across the compiler stack.
- Optimize compilation for dataflow architectures through pipelined scheduling, memory orchestration, and resource-constrained execution strategies.
- Collaborate with hardware architects to shape accelerator features, instruction sets, execution models, and compiler–hardware co-design.
- Develop compilation strategies that combine analog compute with digital subsystems.
- Build and maintain a compiler that produces high-performance binaries with strong debugging support, clear error messages, and predictable performance models.
Requirements
- At least 3 years of experience building compilers or high-performance systems software, particularly involving complex resource management or optimization.
- Expertise in modern C++ and strong Python skills.
- Experience with SSA-based or graph-based compiler IRs, transformations, and code generation.
- Exposure to specialized accelerators such as GPUs, NPUs, FPGAs, or custom ASICs, or to parallel architectures.
Benefits
- Opportunity to shape compilation of deep learning and LLM workloads on novel hardware.
- Role spanning software and hardware co-design, including accelerator architecture.
- Collaborative environment focused on engineering rigor, continuous integration, user-focused design, shared learning, and technical excellence.
- Competitive compensation, equity, and benefits package.
