Senior Software Engineer - Low Power Verification
Cadence Design Systems2 months ago
Zhubei, TaiwanSenior
Responsibilities
- Improve the performance and correctness of UPF waveform generation across the Parallel Partition Compiler and Modular Compiler flows, including Dielet UPF support.
- Improve SAGE-based UPF debugging with Verisium for better performance and usability.
- Develop AI-assisted, Verisium-integrated UPF debugging tools to reduce time-to-root-cause for low-power design issues.
- Work with R&D, PE, and AE teams to deploy UPF solutions across AVIP, UVMA, Modular Compiler, and Dielet flows in 2-state and 4-state environments.
- Help consolidate and unify UPF debugging across Palladium and Protium.
Requirements
- Bachelor’s degree in computer science, electrical engineering, or a related field with 4+ years of experience; alternatively, a master’s degree with 2+ years, a PhD with 1+ year, or equivalent practical experience.
- Working knowledge of IEEE 1801 UPF and RTL languages including Verilog, SystemVerilog, and VHDL.
- Strong debugging and root-cause analysis skills using logs, waveforms, traces, test cases, and user reports.
- Ability to read, review, and reason about C++ code and object-oriented designs.
- Scripting experience in Perl, Tcl/Tk, and/or Python.
- Fluency with AI-assisted coding tools such as Copilot, Claude, or Cursor, including critical evaluation of AI output.
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.