2 months ago
Base Salary
$240k - $275k/yr
Responsibilities
- Own MLIR dialect design and lowering passes for the AI accelerator.
- Define high-level tensor IR, async and streaming semantics, and sharded-tensor types bridging ML frameworks to silicon.
- Develop AI-assisted tool flows to accelerate compiler development.
- Work with chip-design and software teams from first silicon through scale-out.
Requirements
- 5+ years of compiler engineering experience with hands-on MLIR contributions or equivalent IR-design experience.
- Exceptional ability in MLIR dialect design, lowering pass authoring, and rewrite patterns.
- Deep understanding of tensor compilation, distributed or sharded execution, and async or streaming dataflow models.
- Strong C++ fluency and experience integrating with ML frameworks such as PyTorch, JAX, ONNX, or TensorFlow.
- Optional qualifications include LLVM backend experience, GPU compiler experience with Triton, IREE, or XLA, and open-source MLIR or LLVM contributions.
Benefits
- Equity grant per company guidelines.
- Medical, dental, and vision benefits.
- 401(k).
- Standard paid time off.
- California base salary range of $240,000–$275,000.
- DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas; work authorization is required at start and immigration support is provided to secure or transfer status.
About DensityAI
DensityAI designs AI accelerator chips and a complete stack—from silicon and boards to racks and software—for training and inference in data-center environments. The privately held company is headquartered in Mountain View, CA, and targets cloud providers and enterprises building scalable AI infrastructure. Its programs span first-silicon bring-up through scale-out systems, with roles across hardware design, verification, and systems software.