Template Job
Astera Labs2 months ago
Base Salary
$207k - $230k/yr
Responsibilities
- Design, implement, and maintain AI/ML system simulators and fabric models covering communication, transport, topology, congestion, routing, buffering, scheduling, and traffic management.
- Improve simulator fidelity, scalability, debuggability, and runtime performance across packet-level, flow-level, and analytical backends.
- Calibrate and validate models against benchmark data and measured silicon across scale-up fabric generations.
- Develop transaction-level, cycle-approximate, theoretical roofline, and analytical models for the Scale-Up Fabric.
- Model collective communication patterns, advanced congestion control, in-network computing, and resiliency at scale.
- Evaluate fabric performance and topology choices as clusters scale from tens to thousands of GPUs.
- Identify architectural bottlenecks and propose solutions in the in-house network model.
- Analyze competing fabric architectures and emerging interconnect technologies, including UALink, ESUN, and optical fabrics.
- Translate modeling insights into architectural proposals, patentable IP, roadmap decisions, and future switch features.
- Partner with ASIC architects and product teams, support early customer engagement, and produce modeling reports, white papers, and presentations.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- 8+ years of relevant experience in network modeling, system architecture, and scale-up fabric benchmarking and analysis.
- Strong programming skills in Python and/or C++ for building and analyzing system models.
- Hands-on experience with cycle-approximate or event-driven system modeling and simulation.
- Deep experience designing, enhancing, and maintaining fabric models with established or in-house simulation frameworks.
- Solid understanding of high-speed interconnect and switching fundamentals, including the physical layer, and protocols such as PCIe, ESUN, UEC, or UALink.
- Experience characterizing bandwidth, latency, buffering, and congestion performance in network models or clusters.
- Preferred: MS or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- Preferred: familiarity with AI/ML collective communication and large-scale LLM training and inference traffic patterns.
- Preferred: experience correlating models against emulation or silicon measurements and analyzing competitive or emerging fabric architectures.
- Preferred: strong communication skills and a record of influencing architectural decisions or contributing to IP and patents.
Benefits
- Eligibility for discretionary bonus, incentives, and benefits.
About Astera Labs
Astera Labs builds semiconductor-based connectivity solutions and software that link CPUs, GPUs, memory, and storage for AI and cloud data centers, integrating CXL, PCIe, Ethernet, NVLink, and UALink. It offers standards-based and custom connectivity products alongside its COSMOS software suite, serving hyperscalers and server OEMs. Founded in 2017 and headquartered in San Jose, it is a public company listed on Nasdaq under the ticker ALAB.