Product Applications Engineer (NCG 2026)
Astera Labs3 months ago
Base Salary
$140k - $150k/yr
Responsibilities
- Assist with customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms.
- Develop, validate, and debug firmware in C and Python across Leo PCIe/CXL and DDR memory subsystems.
- Support end-to-end validation of DDR4/DDR5 DRAM interfaces, including initialization, training, RAS features, and performance tuning.
- Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools for validation and customer debugging.
- Collaborate with firmware engineering, hardware, systems, and product management teams to deliver firmware releases and customer collateral.
- Create technical documentation including application notes, release notes, design guides, and customer-facing collateral.
- Provide technical guidance to customers, address design challenges, and communicate product and process improvement feedback internally.
Requirements
- Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field.
- Proficiency in C for embedded firmware development in RTOS environments.
- Proficiency in Python for scripting, test automation, and diagnostic tooling.
- Knowledge of firmware bring-up, debugging, and validation for memory or I/O subsystems on server platforms.
- Strong debugging skills for triaging and root-causing issues in complex embedded systems.
- Familiarity with SoC interfaces, including DDR controllers, PCIe controllers, and on-chip memory subsystems.
- Knowledge of developer workflows including source code management, preferably Git, code reviews, and CI/CD pipelines.
- Technical writing skills for application notes and other internal and customer-facing documentation.
- Working knowledge of CXL 1.1, 2.0, or 3.0, including memory expansion, pooling, and sharing concepts, is preferred.
- Experience with PCIe endpoint firmware, PCIe protocol layers, enumeration, MSI/MSI-X, SR-IOV, and error handling is preferred.
- Knowledge of DDR4 and/or DDR5 interfaces, initialization, training, timing margins, and ECC/RAS features is preferred.
- Hands-on experience with PCIe/CXL protocol analyzers, BERT, and other laboratory debug equipment is preferred.
- Familiarity with BIOS, BMC, and operating-system interactions with PCIe/CXL devices and MMIO/RAS concepts is preferred.
- Experience with server memory performance tuning is preferred.
- Prior customer-facing or field applications experience in a semiconductor or systems company is a strong plus.
- Must be authorized to work in the United States and available to start immediately.
Benefits
- Required onsite work in San Jose, California.
About Astera Labs
Astera Labs builds semiconductor-based connectivity solutions and software that link CPUs, GPUs, memory, and storage for AI and cloud data centers, integrating CXL, PCIe, Ethernet, NVLink, and UALink. It offers standards-based and custom connectivity products alongside its COSMOS software suite, serving hyperscalers and server OEMs. Founded in 2017 and headquartered in San Jose, it is a public company listed on Nasdaq under the ticker ALAB.