Lead Software Engineer: AI for Hardware Verification
Cadence Design Systems2 days ago
Base Salary
$119k - $221k/yr
Responsibilities
- Design and develop AI-enabled software components for emulation and prototyping workflows while balancing reliability, maintainability, security, latency, cost, and architectural integration.
- Build LLM-based agents, RAG workflows, and automation services for design bring-up, verification, debug, and validation.
- Apply secure and responsible AI practices, including data protection, access control, prompt-injection awareness, safe tool use, auditability, and sensitive-data handling.
- Create testing, evaluation, and observability workflows covering regression tests, retrieval quality, model-output review, tracing, and failure analysis.
- Serve as a technical resource for peers and less-experienced engineers and collaborate with internal partners, senior individual contributors, and managers.
Requirements
- Bachelor’s degree in Computer Science, Computer Engineering, Electrical Engineering, or equivalent experience; typically 4+ years with a Bachelor’s, 2+ years with a Master’s, or PhD-level preparation in related software development.
- Strong Python skills and software engineering fundamentals, including APIs, testing, debugging, maintainability, Unix/Linux environments, and distributed development workflows.
- Hands-on experience building AI-enabled applications, agentic workflows, or automation services using LLM APIs, open-source models, enterprise AI platforms, and orchestration tools such as LangGraph, LangChain, AutoGen, CrewAI, or similar frameworks.
- Understanding of RAG and agentic AI patterns, including retrieval, chunking, embeddings, vector or hybrid search, reranking, tool calling, workflow orchestration, human-in-the-loop review, and traceability.
- Ability to evaluate, secure, and debug AI product behavior using golden datasets, regression tests, hallucination checks, prompt and retrieval analysis, observability traces, quality metrics, and responsible AI practices.
- Experience with version control systems and modern CI/CD practices is preferred.
- Experience with C++, Tcl, or JavaScript/TypeScript is preferred.
- Knowledge of design verification, emulation, prototyping, hardware-assisted debug, EDA, VLSI design, Verilog, SystemVerilog, or VHDL is preferred.
- Exposure to practical AI application security, including prompt-injection awareness, safe tool integration, access control, input/output validation, or secure design-data handling is preferred.
Benefits
- Full-time employment at 40 hours per week in San Jose, California.
- Competitive benefits including paid vacation, paid holidays, 401(k) with employer match, employee stock purchase plan, and medical, dental, and vision options.
- Potential eligibility for incentive compensation, bonus, and equity.
Tech Stack
Categories
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.