Lead Software Engineer
Cadence Design Systems1 day ago
Noida, IndiaMid Level / Senior
Responsibilities
- Design, develop, verify, and deploy Verification IP.
- Create functional verification test environments using SystemVerilog and UVM.
- Debug verification environments and protocol-related issues.
- Work with layered protocols including UCIe, PCIe, CXL, Ethernet, and UALink.
- Collaborate cross-functionally and interact closely with customers.
- Adapt independently to new technologies and protocols.
Requirements
- 4 to 6 years of domain experience.
- Proficiency in functional verification and SystemVerilog/UVM test environment creation with strong debugging skills.
- Hands-on knowledge of C, C++, and scripting.
- Working experience with UCIe, PCIe, CXL, Ethernet, and UALink protocols.
- Strong digital electronics and programming fundamentals.
- BE, BTech, ME, MS, or MTech in Electrical or Electronics.
- Prior Verification IP usage and development experience is a plus.
- Strong analytical, communication, adaptability, collaboration, and problem-solving skills.
Benefits
- Employee-friendly policies supporting physical and mental well-being.
- Career development, learning, and professional development opportunities.
- Collaborative One Cadence – One Team culture.
- Diverse team environment with recognition and opportunities to celebrate success.
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.