Software Engineer II: Hardware Verification R&D
Cadence Design Systems2 months ago
Belo Horizonte, BrazilMid Level
Responsibilities
- Develop new features for the ATPG/DFT and Fault Emulation products, including specifications, C++ implementation, unit tests, regression tests, static analysis, performance evaluation, and code reviews.
- Maintain existing features through bug fixes, refactoring, and performance improvements.
- Collaborate with Application Engineering to support deployment of features on customer systems.
- Work with Product Engineering and Product Validation teams to specify and test features.
Requirements
- Bachelor's degree in computer science or computer engineering, or equivalent experience.
- Two years of software development experience.
- Knowledge and experience with object-oriented programming.
- Knowledge of Git, Perforce, and similar tools.
- Advanced knowledge of data structures and algorithms.
- Knowledge of C++ programming.
- Experience with a Unix environment.
- Very good spoken and written English and Portuguese.
- Preferred experience with compilers and scripting environments such as Tcl or Python.
- Preferred knowledge or experience with EDA and VLSI design, including Verilog and VHDL.
- Preferred knowledge of DFT/ATPG flows and ISO26262.
Benefits
- Competitive benefits.
- Full-time CLT employment at 40 hours per week.
- On-site position in Belo Horizonte, Minas Gerais, Brazil.
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.