Software Engineer II: Hardware Verification Compiler
Cadence Design Systems1 day ago
Belo Horizonte, BrazilMid Level
Responsibilities
- Develop maintainable, high-quality C/C++ code for an HDL language-based compiler and runtime support.
- Develop the SystemVerilog compiler front end.
- Improve compiler performance, infrastructure, and flows.
- Work with RTL simulation, synthesis, and runtime environments.
- Collaborate across geographies and contribute to product enhancements.
Requirements
- Completed bachelor’s degree in computer science, computer engineering, or a related field with 3+ years of experience, or a completed master’s degree in one of these fields.
- Work experience with C/C++ programming.
- Knowledge and expertise in compilers.
- Knowledge and experience with object-oriented programming.
- Advanced knowledge of data structures and algorithms.
- Experience with the Unix environment.
- Very good spoken and written English and Portuguese.
- Preferred experience with version control systems, Tcl or Python scripting, formal verification or simulation, and EDA/VLSI design including Verilog, SystemVerilog, and VHDL.
Benefits
- Competitive benefits.
- CLT employment category with a 40-hour workweek.
- On-site location at Av Contorno 5800, Belo Horizonte, Minas Gerais, Brazil.
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.