Principal Product Application Engineer - Leo
Astera Labs5 months ago
Base Salary
$175k - $230k/yr
Responsibilities
- Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms.
- Develop, validate, and debug firmware using C and Python across Leo’s PCIe/CXL and DDR memory subsystems.
- Lead requirements discussions for DDR4/DDR5 DRAM interfaces, including initialization, training, RAS features, and performance tuning.
- Act as the primary firmware technical contact for key hyperscaler and OEM accounts, driving issue resolution and feature demonstrations.
- Interpret CXL, PCIe, and JEDEC DDR specifications and implement them in firmware solutions.
- Collaborate with firmware, hardware, systems, and product management teams to deliver firmware releases and customer collateral.
- Develop and maintain Python-based test scripts, automation frameworks, and diagnostic tools for validation and customer debugging.
- Create application notes, release notes, design guides, and other customer-facing technical documentation.
- Represent the Leo team in customer technical reviews, design-in engagements, and industry forums.
Requirements
- Bachelor’s degree in Electrical Engineering, Computer Science, or a related technical field is required; a master’s degree is preferred.
- 8+ years of experience in firmware development, product applications engineering, or a related technical role supporting complex SoC or silicon products for server, storage, or networking applications.
- High proficiency in C for embedded firmware development in RTOS environments.
- Working knowledge of CXL 1.1, 2.0, and 3.0, including memory expansion, pooling, and sharing concepts.
- Proficiency in Python for scripting, test automation, and diagnostic tooling.
- Deep hands-on knowledge of DDR4 and/or DDR5 DRAM interfaces, including initialization, training algorithms, timing margins, and ECC/RAS features.
- Experience bringing up, debugging, and validating memory or I/O subsystems on server platforms.
- Strong debugging skills for triaging and root-causing issues in complex embedded systems.
- Familiarity with SoC interfaces including DDR controllers, PCIe controllers, and on-chip memory subsystems.
- Experience with SCM, preferably Git, code reviews, and CI/CD pipelines.
- Preferred experience includes PCIe endpoint firmware at the PHY, Link, and Transaction layers, including PCIe enumeration, MSI/MSI-X, SR-IOV, and error handling.
- Preferred experience includes PCIe/CXL protocol analyzers, BERT, lab debug equipment, BIOS/BMC/OS interactions, MMIO/RAS concepts, and server memory performance tuning.
- Prior customer-facing or field applications experience in a semiconductor or systems company is preferred.
- Must be authorized to work in the United States and available to start immediately.
Benefits
- Required onsite work in San Jose, California.
- Immediate start availability is requested.
- Equal opportunity employer with an inclusive workplace.
About Astera Labs
Astera Labs builds semiconductor-based connectivity solutions and software that link CPUs, GPUs, memory, and storage for AI and cloud data centers, integrating CXL, PCIe, Ethernet, NVLink, and UALink. It offers standards-based and custom connectivity products alongside its COSMOS software suite, serving hyperscalers and server OEMs. Founded in 2017 and headquartered in San Jose, it is a public company listed on Nasdaq under the ticker ALAB.