Lead Software Engineer - Logic Synthesis
Cadence Design Systems1 day ago
Shanghai, ChinaStaff+
Responsibilities
- Develop and maintain the Palladium synthesizer.
- Implement new VHDL and Verilog feature support in the synthesizer.
- Optimize logic and improve synthesizer performance.
- Collaborate effectively across multi-site and multi-person projects.
Requirements
- Bachelor’s or master’s degree in electrical engineering, computer science, or computer engineering.
- 3–5 years of industry experience.
- Proficiency with C/C++ and operating-system concepts.
- Experience with design modeling using Verilog/SystemVerilog, VHDL, or SystemC.
- Preferred experience with RTL modeling of bus functional models and verification methodologies using UVM and SC/TLM.
- Preferred experience developing EDA/CAD tools or performing logic design verification.
- Preferred knowledge of AI tools such as Copilot or Claude Code.
- Good communication skills, attention to detail, and ability to work in multi-site, multi-person projects.
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.