3 months ago
Sunnyvale, CA, USAStaff+
Base Salary
$189k - $267k/yr
Responsibilities
- Architect multi-stage secure boot chains from immutable mask ROM and primary bootloaders through secondary bootloaders and U-Boot.
- Implement hardware-enforced isolation using NXP xRDC/XRDC4, Memory Protection Units, domain controllers, peripheral access controllers, and fault-domain segregation.
- Develop atomic A/B firmware update schemes, dual-bank partitions, and runtime fallback state machines.
- Design low-latency inter-process and inter-core communication using shared memory, hardware semaphores, and zero-copy data paths.
- Package and deploy block drivers and fault-tolerant flash file systems while implementing wear leveling and delta compression.
- Lead hardware bring-up and lab verification using JTAG/SWD debuggers, logic analyzers, and oscilloscopes.
- Validate memory protections, security states, and peripheral or bus interference.
Requirements
- Experience configuring hardware-based cryptographic enclaves such as HSMs, TPMs, or ARM TrustZone.
- Experience developing secure key storage, device attestation, and anti-rollback protections using eFuses or secure flash memory.
- Experience designing high-performance inter-process and inter-core communication mechanisms with shared memory, hardware semaphores, and zero-copy paths.
- Experience with low-level block drivers, fault-tolerant flash file systems, and storage technologies such as eMMC, UFS, and QSPI.
- Ability to write deterministic embedded C for resource-constrained environments with freedom from interference and tight task-scheduling control.
- Experience defending low-level execution paths against voltage manipulation, clock glitching, and side-channel access.
- Experience with low-level hardware integration, bring-up, debugging, and validation in the lab.
