Software Engineer II: Hardware Verification Compiler
Cadence Design Systems4 days ago
Belo Horizonte, BrazilMid Level
Responsibilities
- Develop compiler technology for the Cadence Palladium Platform.
- Design and implement scalable software for large compile workloads, including model checking and structural checking.
- Improve compiler functionality, scalability, and performance.
- Apply multithreading and distributed-computing techniques to large-scale compilation problems.
- Develop, debug, test, and maintain production-quality C/C++ software in a Linux/Unix environment.
- Collaborate with local and global engineering teams on design, implementation, validation, and issue resolution.
Requirements
- Complete a bachelor’s degree or master’s degree in engineering, computer science, or a related field.
- Professional experience with strong understanding of data structures, algorithms, and databases.
- Demonstrated proficiency in C++, gdb debugging, and general software development.
- Familiarity with Linux/Unix development.
- Exposure to build and version-control systems.
- Coursework in hardware description languages such as Verilog, SystemVerilog, or VHDL.
- Exposure to electronic design platforms.
- Strong communication skills in English and Portuguese.
Benefits
- Competitive benefits.
- CLT employment category.
- 40-hour workweek.
- On-site position in Belo Horizonte, Minas Gerais, Brazil.
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.