Product Engineering Architect (3D IC, Heterogeneous Integration & Advanced Packaging)
Cadence Design Systems2 days ago
Base Salary
$186k - $345k/yr
Responsibilities
- Drive, validate, and promote end-to-end system design implementation flows spanning 3D IC, heterogeneous integration, and advanced packaging.
- Lead strategic customer engagements involving advanced heterogeneous integration and multi-die co-design methodologies.
- Shape product roadmap direction using customer requirements, market trends, competitive insights, and technical feasibility.
- Produce Product Requirement Specifications, technical use cases, demonstrations, application workflows, and enablement materials.
- Provide technical leadership through trade-off analysis, solution validation, adoption risk assessment, and prioritization of bugs and enhancements.
- Mentor product engineers and cross-functional team members on design-flow challenges, technical decisions, and customer communication.
- Represent product engineering in roadmap discussions, customer reviews, product launches, and industry events.
- Own deliverables from definition through customer deployment and collaborate with R&D, Product Management, Field teams, Technical Publications, and Product Validation.
Requirements
- Bachelor's degree in Electrical Engineering, Electronics, or a related technical field.
- 15+ years of relevant experience in product engineering, methodology development, customer enablement, or technical leadership.
- Deep expertise in semiconductor design, physical implementation, advanced packaging, or EDA product engineering.
- Strong hands-on knowledge of the Cadence Virtuoso platform and associated custom IC design flows.
- Demonstrated ability to shape technical direction, align cross-functional stakeholders, and drive team-level technical objectives.
- Proven experience with strategic customers, complex requirements discovery, executive-level technical communication, and deployment of advanced design flows.
- Experience with 3D IC, heterogeneous integration, and silicon-package-board co-design flows is preferred.
- Knowledge of Cadence Allegro Package Designer Plus and package implementation methodologies is preferred.
- Knowledge of Cadence Virtuoso SKILL or another interpreted language is preferred.
- Strong verbal and written communication skills and ability to work across global, multicultural, and cross-functional teams.
Benefits
- Annual salary range of $185,500 to $344,500, with potential incentive compensation, bonus, equity, and benefits.
- Paid vacation and paid holidays.
- 401(k) plan with employer match.
- Employee stock purchase plan.
- Medical, dental, and vision plan options.
- Approximately 5-10% travel, primarily for strategic customer engagements and internal collaboration.
- Located in San Jose, California.
Categories
Solutions Engineering
About Cadence Design Systems
Cadence Design Systems builds electronic design automation (EDA) software, emulation/acceleration hardware, and reusable IP that help semiconductor and systems companies design, verify, and implement chips and electronic systems. It also develops computational engineering tools, including computational fluid dynamics and molecular modeling for drug discovery. Founded in 1988 and headquartered in San Jose, California, Cadence is a public company listed on NASDAQ under the ticker CDNS.