Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions
Cadence Design SystemsResponsibilities
- Drive development and deployment of advanced timing, power, signal integrity, and ECO signoff methodologies.
- Develop and optimize MMMC timing closure methodologies and signoff correlation across implementation, STA, SPICE, and signoff environments.
- Lead qualification and certification activities for advanced-node design flows.
- Support customer tapeouts and critical milestones through root-cause analysis, debugging, and resolution of design-closure challenges.
- Define and validate setup and hold closure, power optimization, crosstalk mitigation, glitch fixing, electrical-rule fixing, and multi-view timing closure methodologies.
- Partner with customers, R&D, application engineering, and field engineering teams to resolve complex technical challenges and prioritize product enhancements.
- Create deployment collateral, technical presentations, and best-practice methodologies.
- Lead strategic customer engagements, technical reviews, escalations, mentoring, and cross-functional execution.
- Drive adoption of AI-assisted signoff and ECO automation technologies.
Requirements
- 8–12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering.
- Strong expertise in static timing analysis, MMMC timing analysis, signoff convergence, statistical timing analysis, signal integrity, crosstalk, glitch analysis, ECO closure, timing and SPICE correlation, power optimization, boundary-model and hierarchical timing flows, RC extraction, parasitic analysis, and physical implementation signoff optimization.
- Hands-on experience supporting advanced-node ASIC or SoC designs through implementation, timing closure, ECO convergence, and tapeout.
- Proven experience working directly with semiconductor customers, R&D organizations, and field engineering teams.
- Experience developing and deploying production signoff methodologies across multiple technology nodes and large-scale designs.
- Experience leading technical investigations, root-cause analysis, customer engagements, and product enhancements.
- Preferred experience with 7nm, 5nm, 3nm, 2nm or beyond technologies; designs exceeding 100 million instances; hierarchical signoff; PPA optimization; ECO closure; signal integrity; glitch fixing; timing correlation; and AI-assisted implementation and signoff workflows.
- Experience with Cadence Tempus, PrimeTime, Innovus, ICC, FC, and Tempus ECO/Tweaker is desired.
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About Cadence Design Systems
Cadence is a market leader in AI and digital twins, pioneering the application of computational software to accelerate innovation in the engineering design of silicon to systems. Our design solutions, based on Cadence’s Intelligent System Design™ strategy, are essential for the world’s leading semiconductor and systems companies to build their next-generation products from chips to full electromechanical systems that serve a wide range of markets, including hyperscale computing, mobile communications, automotive, aerospace, industrial, life sciences and robotics. In 2024, Cadence was recognized by the Wall Street Journal as one of the world’s top 100 best-managed companies. Cadence solutions offer limitless opportunities—learn more at www.cadence.com.